1. Field of the Invention
This invention relates to packaged semiconductor devices and methods for manufacture thereof. More particularly, the invention pertains to ultra-thin devices having a small footprint and simplified processes for their manufacture including device packaging at the wafer scale.
2. State of the Art
Solid state electronic devices, more colloquially known as semiconductor chips or dice, are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. Circuitry is formed on one surface of the device with input and output (I/O) pads formed around the periphery or centrally positioned to facilitate electrical connection with a host electrical apparatus.
A profusion of small electronic consumer products includes pagers, notebook computers, cellular telephones, digital cameras, modems, global position systems and electronic watches, to name a few. The rapidly growing consumer demand for small product size and low profile products drives the search for ways to construct smaller, thinner, more powerful semiconductor devices. The development of inexpensive, ultra-thin, compact devices is needed to enable the proliferation of large numbers of miniature electronic apparatus in the near future.
Currently, semiconductor chips are typically packaged to protect the chip from mechanical damage, external contamination and moisture. Most commonly, semiconductor chips are encapsulated, i.e., packaged within a polymeric material which sometimes provides opportunity for moisture ingress, gas diffusion, corrosion, etc. Thus, plastic encapsulated chips may be subject to performance degradation and abbreviated life.
Ceramic encapsulation provides a higher level of protection for the chip. However, the process is more complex and results in an expensive package of increased size.
Sealing of the semiconductor chip active circuitry at the wafer stage is known. In this process, a passivation coating of ceramic materials such as silica and/or silicon nitride may be applied by chemical vapor deposition (CVD). However, the subsequent etching back of the passivation coating at the bond pads of the semiconductor chip may damage the coating around the bond pads, resulting in a non-hermetic seal and permitting corrosion to deleteriously affect chip reliability and life.
U.S. Pat. No. 5,336,928 of Neugebauer et al. discloses a hermetically sealed device construction.
U.S. Pat. Nos. 5,455,459 and 5,497,033 of Fillion et al. disclose systems for enclosing and interconnecting multiple semiconductor chips.
U.S. Pat. No. 5,481,135 of Chandra et al. discloses the use of ceramic materials in hermetically sealed device packages.
U.S. Pat. No. 4,769,345 of Butt et al., U.S. Pat. Nos. 4,866,571, 4,967,260 and 5,014,159 of Butt, U.S. Pat. No. 5,323,051 of Adams et al., and U.S. Pat. No. 4,821,151 of Pryor et al. disclose the use of glass in the packaging of certain types of semiconductor devices.
U.S. Pat. Nos. 4,749,631 and 4,756,977 of Haluska et al. disclose ceramic and ceramic-like compositions which may be used for coating electronic devices.
In U.S. Pat. No. 5,682,065 of Farnworth et al., a fully hermetically sealed semiconductor chip is disclosed. The bare die is covered with a coating of glass using a spin-on-glass (SOG) process, a dip process or flow coating. The glass is applied as a mixture of small glass particles and a polymeric carrier, and subsequently heated to evaporate solvent(s) from the mixture and harden the applied material. Also disclosed are steps of thinning the wafer.
U.S. Pat. No. 5,547,906 of Badehi discloses a method for forming semiconductor chip packages with edge connections. The step of singulation with a cutting tool exposes the array of contacts. A glass may be used as covers for sandwiching the chip therebetween.
The invention comprises a method for fabricating size-efficient semiconductor devices, including hermetically sealed devices, wherein most of the operations are conducted at the wafer scale. The method enables the simplified manufacture of ultra-thin packaged devices, having a footprint only slightly larger than the die size.
A wafer is prepared with multiple die sectors having internal circuits with conductive bond pads. A thin plate of glass is then adhesively attached to the active side of the wafer. The glass is configured for photo-etching, making repatterning of the wafer front side prior to glass overlay unnecessary. Furthermore, scribing of the wafer prior to metallization of the glass plate is unnecessary.
If needed, the exterior surface of the glass plate is leveled and made parallel to the front side (active surface) of the wafer and polished, based on the wafer""s parallel back side. The leveling, paralleling and cleaning of the glass plate prepares the exterior glass surface for metallization.
The back side of the wafer is then reduced in thickness by chemical, mechanical, or chemical-mechanical means, such as are known in the art, to provide chip substrates with minimum thickness. The wafer is then cut or etched in the street areas between the chip sectors to individualize the chips, while leaving intact the upper glass plate to which the chips are individually attached. The glass plate enhances the resistance to premature breakage along the street areas or of the chips themselves.
A second glass plate is then adhesively affixed to the back side of the wafer, the adhesive filling the opened street areas between the chip sectors.
Alternatively, a polymeric sealant material may be applied over the back side of the wafer, instead of adhesively attaching the second plate of glass. In addition, another alternative is applying a mixture of glass particles and polymer, which may be applied in a spin-on-glass process.
On the upper glass plate, contact holes are formed through the glass and adhesive to access the bond pads, using a photolithographic etching process. The glass plate is then metallized and etched to define leads thereon.
Preferably, metallization of the front side of the glass plate is based on palladium or a palladium alloy, which, because of its solder wettability, eliminates the need for a solder mask limiting layer. A chemical vapor deposition (CVD) process or sputtering process deposits the conductive metal in the contact holes and on the glass surface, and a subsequent patterning of the metallization enables the formation of interconnects on the glass surface. Alternately, deposit may be made by wet deposition by first sputtering metal, such as aluminum, etc., then patterning the metal (aluminum), then using a zincate process, applying nickel, then applying a flash plating of palladium, which results in a thicker metal and a lower resistance with less palladium being required.
The chips may then be singulated by, e.g., sawing, and the die of each chip will be entirely closed.
To ensure that the chip is fully hermetically sealed, a coating of silicon nitride may be applied prior to, or following, the step of metallizing the upper glass surface.
In an alternative embodiment of the invention, glass is applied to the front side and/or back side of the wafer as spin-on-glass (SOG), which may be polished flat.